C.4 Store Sequences Result in Unnecessary Stalls
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C.4 Store Sequences Result in Unnecessary Stalls

Unfortunately, each store buffer must be relatively small, which means that a CPU executing a modest sequence of stores can fill its store buffer (for example, if all of them result in cache misses). At that point, the CPU must once again wait for invalidations to complete in order to drain its store buffer before it can continue executing. This same situation can arise immediately after a memory barrier, when all subsequent store instructions must wait for invalidations to complete, regardless of whether or not these stores result in cache misses.

This situation can be improved by making invalidate acknowledge messages arrive more quickly. One way of accomplishing this is to use per-CPU queues of invalidate messages, or ``invalidate queues''.

Subsections

- C.4.1 Invalidate Queues
- C.4.2 Invalidate Queues and Invalidate Acknowledge
- C.4.3 Invalidate Queues and Memory Barriers