C.2.1 MESI States
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C.2.1 MESI States

MESI stands for ``modified'', ``exclusive'', ``shared'', and ``invalid'', the four states a given cache line can take on using this protocol. Caches using this protocol therefore maintain a two-bit state ``tag'' on each cache line in addition to that line's physical address and data.

A line in the ``modified'' state has been subject to a recent memory store from the corresponding CPU, and the corresponding memory is guaranteed not to appear in any other CPU's cache. Cache lines in the ``modified'' state can thus be said to be ``owned'' by the CPU. Because this cache holds the only up-to-date copy of the data, this cache is ultimately responsible for either writing it back to memory or handing it off to some other cache, and must do so before reusing this line to hold other data.

The ``exclusive'' state is very similar to the ``modified'' state, the single exception being that the cache line has not yet been modified by the corresponding CPU, which in turn means that the copy of the cache line's data that resides in memory is up-to-date. However, since the CPU can store to this line at any time, without consulting other CPUs, a line in the ``exclusive'' state can still be said to be owned by the corresponding CPU. That said, because the corresponding value in memory is up to date, this cache can discard this data without writing it back to memory or handing it off to some other CPU.

A line in the ``shared'' state might be replicated in at least one other CPU's cache, so that this CPU is not permitted to store to the line without first consulting with other CPUs. As with the ``exclusive'' state, because the corresponding value in memory is up to date, this cache can discard this data without writing it back to memory or handing it off to some other CPU.

A line in the ``invalid'' state is empty, in other words, it holds no data. When new data enters the cache, it is placed into a cache line that was in the ``invalid'' state if possible. This approach is preferred because replacing a line in any other state could result in an expensive cache miss should the replaced line be referenced in the future.

Since all CPUs must maintain a coherent view of the data carried in the cache lines, the cache-coherence protocol provides messages that coordinate the movement of cache lines through the system.