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#### 14.2.4.4.1 Pairing 1.

In this pairing, one CPU executes a pair of loads separated by a memory barrier, while a second CPU executes a pair of stores also separated by a memory barrier, as follows (both A and B are initially equal to zero):

`CPU 1` | `CPU 2`
`A=1;` | `Y=B;`
`smp_mb();` | `smp_mb();`
`B=1;` | `X=A;`

After both CPUs have completed executing these code sequences, if Y==1, then we must also have X==1. In this case, the fact that Y==1 means that CPU 2's load prior to its memory barrier has seen the store following CPU 1's memory barrier. Due to the pairwise nature of memory barriers, CPU 2's load following its memory barrier must therefore see the store that precedes CPU 1's memory barrier, so that Y==1.

On the other hand, if Y==0, the memory-barrier condition does not hold, and so in this case, X could be either 0 or 1.