14.2.10 What Are Memory Barriers?
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14.2.10 What Are Memory Barriers?

As can be seen above, independent memory operations are effectively performed in random order, but this can be a problem for CPU-CPU interaction and for I/O. What is required is some way of intervening to instruct the compiler and the CPU to restrict the order.

Memory barriers are such interventions. They impose a perceived partial ordering over the memory operations on either side of the barrier.

Such enforcement is important because the CPUs and other devices in a system can use a variety of tricks to improve performance - including reordering, deferral and combination of memory operations; speculative loads; speculative branch prediction and various types of caching. Memory barriers are used to override or suppress these tricks, allowing the code to sanely control the interaction of multiple CPUs and/or devices.

Subsections

- 14.2.10.1 Explicit Memory Barriers
  - 14.2.10.1.1 Write Memory Barriers
  - 14.2.10.1.2 Data Dependency Barriers
  - 14.2.10.1.3 Read Memory Barriers
  - 14.2.10.1.4 General Memory Barriers
- 14.2.10.2 Implicit Memory Barriers
  - 14.2.10.2.1 LOCK Operations
  - 14.2.10.2.2 UNLOCK Operations
- 14.2.10.3 What May Not Be Assumed About Memory Barriers?
- 14.2.10.4 Data Dependency Barriers
- 14.2.10.5 Control Dependencies
- 14.2.10.6 SMP Barrier Pairing
- 14.2.10.7 Examples of Memory Barrier Pairings
- 14.2.10.8 Read Memory Barriers vs. Load Speculation