C.2.2 MESI Protocol Messages
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C.2.2 MESI Protocol Messages

Many of the transitions described in the previous section require communication among the CPUs. If the CPUs are on a single shared bus, the following messages suffice:

- Read: The ``read'' message contains the physical address of the cache line to be read.
- Read Response: The ``read response'' message contains the data requested by an earlier ``read'' message. This ``read response'' message might be supplied either by memory or by one of the other caches. For example, if one of the caches has the desired data in ``modified'' state, that cache must supply the ``read response'' message.
- Invalidate: The ``invalidate'' message contains the physical address of the cache line to be invalidated. All other caches must remove the corresponding data from their caches and respond.
- Invalidate Acknowledge: A CPU receiving an ``invalidate'' message must respond with an ``invalidate acknowledge'' message after removing the specified data from its cache.
- Read Invalidate: The ``read invalidate'' message contains the physical address of the cache line to be read, while at the same time directing other caches to remove the data. Hence, it is a combination of a ``read'' and an ``invalidate'', as indicated by its name. A ``read invalidate'' message requires both a ``read response'' and a set of ``invalidate acknowledge'' messages in reply.
- Writeback: The ``writeback'' message contains both the address and the data to be written back to memory (and perhaps ``snooped'' into other CPUs' caches along the way). This message permits caches to eject lines in the ``modified'' state as needed to make room for other data.

Interestingly enough, a shared-memory multiprocessor system really is a message-passing computer under the covers. This means that clusters of SMP machines that use distributed shared memory are using message passing to implement shared memory at two different levels of the system architecture.

Quick Quiz C.1: What happens if two CPUs attempt to invalidate the same cache line concurrently? End Quick Quiz

Quick Quiz C.2: When an ``invalidate'' message appears in a large multiprocessor, every CPU must give an ``invalidate acknowledge'' response. Wouldn't the resulting ``storm'' of ``invalidate acknowledge'' responses totally saturate the system bus? End Quick Quiz

Quick Quiz C.3: If SMP machines are really using message passing anyway, why bother with SMP at all? End Quick Quiz