C. Why Memory Barriers?
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C. Why Memory Barriers?

So what possessed CPU designers to cause them to inflict memory barriers on poor unsuspecting SMP software designers?

In short, because reordering memory references allows much better performance, and so memory barriers are needed to force ordering in things like synchronization primitives whose correct operation depends on ordered memory references.

Getting a more detailed answer to this question requires a good understanding of how CPU caches work, and especially what is required to make caches really work well. The following sections:

1. present the structure of a cache,
2. describe how cache-coherency protocols ensure that CPUs agree on the value of each location in memory, and, finally,
3. outline how store buffers and invalidate queues help caches and cache-coherency protocols achieve high performance.

We will see that memory barriers are a necessary evil that is required to enable good performance and scalability, an evil that stems from the fact that CPUs are orders of magnitude faster than are both the interconnects between them and the memory they are attempting to access.

Subsections

- C.1 Cache Structure
- C.2 Cache-Coherence Protocols
  - C.2.1 MESI States
  - C.2.2 MESI Protocol Messages
  - C.2.3 MESI State Diagram
  - C.2.4 MESI Protocol Example
- C.3 Stores Result in Unnecessary Stalls
  - C.3.1 Store Buffers
  - C.3.2 Store Forwarding
  - C.3.3 Store Buffers and Memory Barriers
- C.4 Store Sequences Result in Unnecessary Stalls
  - C.4.1 Invalidate Queues
  - C.4.2 Invalidate Queues and Invalidate Acknowledge
  - C.4.3 Invalidate Queues and Memory Barriers
- C.5 Read and Write Memory Barriers
- C.6 Example Memory-Barrier Sequences
  - C.6.1 Ordering-Hostile Architecture
  - C.6.2 Example 1
  - C.6.3 Example 2
  - C.6.4 Example 3
- C.7 Memory-Barrier Instructions For Specific CPUs
  - C.7.1 Alpha
  - C.7.2 AMD64
  - C.7.3 ARMv7-A/R
  - C.7.4 IA64
  - C.7.5 PA-RISC
  - C.7.6 POWER / Power PC
  - C.7.7 SPARC RMO, PSO, and TSO
  - C.7.8 x86
  - C.7.9 zSeries
- C.8 Are Memory Barriers Forever?
- C.9 Advice to Hardware Designers