C.6 Example Memory-Barrier Sequences
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C.6 Example Memory-Barrier Sequences

This section presents some seductive but subtly broken uses of memory barriers. Although many of them will work most of the time, and some will work all the time on some specific CPUs, these uses must be avoided if the goal is to produce code that works reliably on all CPUs. To help us better see the subtle breakage, we first need to focus on an ordering-hostile architecture.

Subsections

- C.6.1 Ordering-Hostile Architecture
- C.6.2 Example 1
- C.6.3 Example 2
- C.6.4 Example 3