4. Hardware and its Habits
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4. Hardware and its Habits

Most people have an intuitive understanding that passing messages between systems is considerably more expensive than performing simple calculations within the confines of a single system. However, it is not always so clear that communicating among threads within the confines of a single shared-memory system can also be quite expensive. This chapter therefore looks the cost of synchronization and communication within a shared-memory system. This chapter merely scratches the surface of shared-memory parallel hardware design; readers desiring more detail would do well to start with a recent edition of Hennessy and Patterson's classic text [HP95].

Quick Quiz 4.1: Why should parallel programmers bother learning low-level properties of the hardware? Wouldn't it be easier, better, and more general to remain at a higher level of abstraction? End Quick Quiz

Subsections

- 4.1 Overview
  - 4.1.1 Pipelined CPUs
  - 4.1.2 Memory References
  - 4.1.3 Atomic Operations
  - 4.1.4 Memory Barriers
  - 4.1.5 Cache Misses
  - 4.1.6 I/O Operations
- 4.2 Overheads
  - 4.2.1 Hardware System Architecture
  - 4.2.2 Costs of Operations
- 4.3 Hardware Free Lunch?
  - 4.3.1 3D Integration
  - 4.3.2 Novel Materials and Processes
  - 4.3.3 Special-Purpose Accelerators
  - 4.3.4 Existing Parallel Software
- 4.4 Software Design Implications