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#### 14.2.4.4.3 Pairing 3.

In this pairing, one CPU executes a load followed by a memory barrier followed by a store, while the other CPU executes a pair of stores separated by a memory barrier, as follows (both A and B are initially equal to zero):

`CPU 1` | `CPU 2`
`X=A;` | `B=2;`
`smp_mb();` | `smp_mb();`
`B=1;` | `A=1;`

After both CPUs have completed executing these code sequences, if X==1, then we must also have B==1. In this case, the fact that X==1 means that CPU 1's load prior to its memory barrier has seen the store following CPU 2's memory barrier. Due to the pairwise nature of memory barriers, CPU 1's store following its memory barrier must therefore see the results of CPU 2's store preceding its memory barrier. This means that CPU 1's store to B will overwrite CPU 2's store to B, resulting in B==1.

On the other hand, if X==0, the memory-barrier condition does not hold, and so in this case, B could be either 1 or 2.