Keywords: perfbook_html

#### 14.2.4.5.2 Stores ``Pass in the Night''.

In the following example, after both CPUs have finished executing their code sequences, it is quite tempting to conclude that the result `{A==1,B==2}` cannot happen.

`CPU 1` | `CPU 2`
`A=1;` | `B=2;`
`smp_mb();` | `smp_mb();`
`B=1;` | `A=2;`

Unfortunately, such a conclusion does not necessarily hold on all 20th-century systems. Suppose that the cache line containing A is initially owned by CPU 2, and that containing B is initially owned by CPU 1. Then, in systems that have invalidation queues and store buffers, it is possible for the first assignments to ``pass in the night'', so that the second assignments actually happen first. This strange (but quite common) effect is explained in Appendix .

This same effect can happen in any memory-barrier pairing where each CPU's memory barrier is preceded by a store, including the ``ears to mouths'' pairing.

However, 21st-century hardware does accommodate ordering intuitions, and do permit this combination to be used safely.