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#### 14.2.4.4.2 Pairing 2.

In this pairing, each CPU executes a load followed by a memory barrier followed by a store, as follows (both A and B are initially equal to zero):

`CPU 1` | `CPU 2`
`X=A;` | `Y=B;`
`smp_mb();` | `smp_mb();`
`B=1;` | `A=1;`

After both CPUs have completed executing these code sequences, if X==1, then we must also have Y==0. In this case, the fact that X==1 means that CPU 1's load prior to its memory barrier has seen the store following CPU 2's memory barrier. Due to the pairwise nature of memory barriers, CPU 1's store following its memory barrier must therefore see the results of CPU 2's load preceding its memory barrier, so that Y==0.

On the other hand, if X==0, the memory-barrier condition does not hold, and so in this case, Y could be either 0 or 1.

The two CPUs' code sequences are symmetric, so if Y==1 after both CPUs have finished executing these code sequences, then we must have X==0.