C.6.3 Example 2
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C.6.3 Example 2

Table shows three code fragments, executed concurrently by CPUs 0, 1, and 2. Both ``a'' and ``b'' are initially zero.

Table: Memory Barrier Example 2
CPU 0 | CPU 1 | CPU 2
a = 1; | while (a == 0); |
| smp_mb(); | y = b;
| b = 1; | smp_rmb();
|  | x = a;
|  | assert(y == 0 || x == 1);

Again, suppose CPU 0 recently experienced many cache misses, so that its message queue is full, but that CPU 1 has been running exclusively within the cache, so that its message queue is empty. Then CPU 0's assignment to ``a'' will appear in Node 0's cache immediately (and thus be visible to CPU 1), but will be blocked behind CPU 0's prior traffic. In contrast, CPU 1's assignment to ``b'' will sail through CPU 1's previously empty queue. Therefore, CPU 2 might well see CPU 1's assignment to ``b'' before it sees CPU 0's assignment to ``a'', causing the assertion to fire, despite the memory barriers.

In theory, portable code should not rely on this example code fragment, however, as before, in practice it actually does work on most mainstream computer systems.