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#### 14.2.10.1.1 Write Memory Barriers

A write memory barrier gives a guarantee that all the STORE operations specified before the barrier will appear to happen before all the STORE operations specified after the barrier with respect to the other components of the system.

A write barrier is a partial ordering on stores only; it is not required to have any effect on loads.

A CPU can be viewed as committing a sequence of store operations to the memory system as time progresses. All stores before a write barrier will occur in the sequence before all the stores after the write barrier.

Note that write barriers should normally be paired with read or data dependency barriers; see the "SMP barrier pairing" subsection.