4.1 Overview
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4.1 Overview

Careless reading of computer-system specification sheets might lead one to believe that CPU performance is a footrace on a clear track, as illustrated in Figure , where the race always goes to the swiftest.

Figure: CPU Performance at its Best

Although there are a few CPU-bound benchmarks that approach the ideal shown in Figure , the typical program more closely resembles an obstacle course than a race track. This is because the internal architecture of CPUs has changed dramatically over the past few decades, courtesy of Moore's Law. These changes are described in the following sections.

Subsections

- 4.1.1 Pipelined CPUs
- 4.1.2 Memory References
- 4.1.3 Atomic Operations
- 4.1.4 Memory Barriers
- 4.1.5 Cache Misses
- 4.1.6 I/O Operations